As a recap, whenever you see the word virtual in computer science, it means "using a level of indirection".
Virtual memory hardware changes the virtual address the programmer sees into the physical one the memory chips see. The reason we want to do this is because we don't want to build $$2^{32}$$ bytes of DRAM that the programmer sees.
This treats memory as a giant cache. As a recap of terminology, blocks have become pages, and a misses are called page faults. This is something that the operating system deals with.
Virtual memory allows us to map a virtual address to a physical one by using a page table: a new data structure accessed by the operating system and hardware stored in memory. The page table has several components. The virtual page address is split into:
The virtual page number returns the physical page number, and the page offset gets you what information that you want. There is a page table register that references the start of the page table.
How big is a page table entry?
How many entries are there in the page table?
Hence, the total size of the page table is $$2^{20} \times 3$$ bytes or 3 MB.
Instead of creating a 3MB page table, you create a multi-level page table! You build a hierarchical page table, keep in physical memory only the translations used. You have a super page table in physical memory, and then second and maybe third level page tables only if needed. The size is proportional to the amount of memory used.
Now, your virtual address consists of:
The beauty of this is that if you don't use a virtual page ever, you never have to allocate memory for it.
Design the virtual memory of a byte addressable processor with 24 bit long addresses. No cache in the system. 256KB of memory installed, and no memory can be added. The virtual memory page is 512B, and each page table entry must be an integer number of bytes, and must be the smallest size required to fit the physical page number + 1 bit to mark a valid entry.
Design a two-level virtual memory system. We want each second-level page table to fit exactly in one memory page, and superpage table entries are 3 bytes each (a memory address poitner to a 2L page table). Compute:
- The number of entries in each second-level page table
- The number of virtual address bits used to index the second-level page table
- The number of virtual address bits used to index the superpage table
- Size of the superpage table.
Since you have 256KB of memory installed, this is $$2^{18}$$ bytes. You need 18 bits to address this. Hence, you know that the length of the physical address is 18 bits long.
You are also told that your virtual address page is 512 bytes. 512 bytes is $$2^9$$ bytes, so your page offset is 9 bytes. Hence, the physical page number is 9 bits. This means that somewhere from your second level page tables, you are getting 9 bits. You also need 1 bit for valid. This brings us to a total of 10 bits. This rounds up to 2 bytes.
You are conveniently told that you want each page table to fit in a single memory page. Hence, you have total 512 bytes for a page, and each line is 2 bytes, so you have 256 lines. If you have 256 individual entries, you need 8 bytes to address it. From earlier, you still have a page offset of 9 bits.
Since each virtual memory address is 24 bits, and the page offset is 9 and the virtual page number is 9. This leaves 7 bits for the super page number. Since each entry is 3 bytes, and 128 entries are 3B each, you need 384B.