Pipeline Exceptions and Performance

Out of order instructions

• Eliminating stall conditions decreases CPI
• Reorder instructions to avoid stalls to wait for two pipelines to sync
• Example:

add 1 2 3
lw 3 2 16
nand 2 6 7
add 4 5 1

vs...

add 1 2 3
lw 3 2 16
add 4 5 1
nand 2 6 7

These are the same, since the instructions do not depend on one another!

Why use this?

• Some instructions take a long time to execute
  • Floating point instructions
  • Some loads and stores
• Options:
  • Increase cycle time
  • Increase number of pipeline stages
  • Execute other instructions while you wait

Calculating performance with data hazards

You just add two cycles of noop after IF, or

Cache Organization Fundamentals

Why does it work out that with memory, you can either get big or get fast but not both? There are two types of RAM, DRAM (a big capacitor), and SRAM. What if you could have things inbetween?